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Open up just about any electronic product and inside will be a Printed Circuit Board (PCB). This board provides the mechanical mounting for the electronic components that make up the design, as well as the electrical connections between them. Having found common use in the electronics industry for over half a century, PCBs have evolved into complex items created by skilled designers and manufactured using precision processes.

While understanding the way a PCB is manufactured is not mandatory for designers, those who have a grasp of the processes involved are far better equipped to design lower cost PCBs that benefit from higher manufacturing yields.

The Anatomy of a PCB

The following sections take a look at various types of PCB - from single-sided, to rigid-flex - and the key elements that are a common factor in the fabrication of all.

Single-Sided Board

The simplest PCB to manufacture is called a single-sided PCB, because it only has conductors on one side; usually the bottom side.

Single-sided PCBs begin their life in much the same way as all PCBs, and that is as an insulating substrate called the Core. The Core can be made from a multitude of materials depending on the desired properties of the final circuit, but the most common material is fiberglass.

The insulating Core is typically fabricated using a material known as FR4. This is Flame Retardant, type 4 woven glass reinforced epoxy laminate - a strong, rigid insulator that retains its high mechanical and electrical insulating properties in both dry and humid conditions, and also has good fabrication properties.

The Core is coated completely on one side with a thin layer of copper. After drilling the holes that will later be used for mounting the components, unwanted copper is removed, using a chemical etching process, to leave the tracks and pads needed to electrically connect the circuit's components together.

The top side of the board is called the Component Side because through-hole components are usually mounted on this side so that their leads protrude through the board to the bottom side, where they can be more easily soldered to the copper pads and tracks. Surface mount components are the exception to this rule since they need to be mounted directly to the copper pads and can only ever exist on the Solder Side.

Double-Sided Board

Only slightly more complex than the single-sided PCB is a double-sided PCB, with copper traces on both the top and bottom sides of the core. This allows for more complex routing.  By convention, through-hole components remain mounted on the Top Layer and surface mount components on the Bottom Layer, as per single-sided PCBs.

Plated Through Holes (PTH)

Double-sided boards typically rely on the leads of through-hole components to provide the electrical connection between top and bottom layers. However this is not always possible, since traces will sometimes need to traverse between the two layers at locations that don't coincide with a component lead. Therefore, a common addition to double-sided PCBs is Plated Through Holes (PTH).

Hole plating is achieved using an electrolysis process to deposit copper inside the hole after it has been drilled. This creates a conduction path between copper on the top and bottom layers, without relying on the lead of a through-hole component.

Top and Bottom Solder Masks

Most PCB assemblies are soldered using either wave or reflow soldering processes. In either case, there is the potential for solder bridging to occur between adjacent traces unless a Solder Mask is applied. The solder mask, as its name implies, provides a repellant (or mask) that helps prevent solder from indiscriminately adhering to copper in areas of the board that would otherwise cause a malfunction. As a secondary benefit, solder masks also prevent the otherwise exposed copper on the PCB traces from corroding.

While just about any color is possible, solder masks have traditionally been colored green and are responsible for the characteristic green that most people recognize PCBs as having. The solder mask is painted onto the top and bottom layers of the PCB using a precision screen printing process.

Silkscreen Layers

When visible information such as company logos, part numbers, or instructions need to be applied to the board, silk screening is used to apply the text to the outer surface of the circuit board. Silk screen information is usually colored white so as to contrast with the chosen solder mask, however any color can be used. Where spacing allows, screened text can indicate component designators, switch setting requirements, and additional features to assist in the assembly process.

Multi-Layered Boards

So far, only PCBs containing one or two copper layers have been described, however it is possible to create PCBs that contain many more layers. These PCBs are called multi-layered PCBs and they can offer much denser routing topologies, as well as better electrical noise characteristics. Each layer within a multi-layered PCB will either be a signal, or plane layer.

• Signal Layers - these layers are reserved entirely for carrying electrical signals from one component to another.
• Plane Layers - these layers are made up of large blocks of copper and are generally used for power supply sources such as VCC and GND. By utilizing a large surface area, plane layers are excellent at preventing and suppressing electrical noise.

Multi-layered PCBs can be manufactured in a couple of different ways but the simplest involves laminating multiple thin, double-sided PCBs together, using a prepreg layer between each.

Prepreg - short for preimpregnated - is a flexible material, typically also containing woven glass, which is supplied to the PCB fabricator partially cured (not completely cooked). It is included between the rigid layers in the layer stack during fabrication, and then heated to perform final curing, after which it becomes rigid, helping to join the layers and form the overall structure of the finished board.

The ratio of double-sided PCBs to prepreg layers can be defined according to cost, weight and electro-mechanical considerations. The following scenarios illustrate variations of layer stack for an example 8-layered board.

1. Scenario 1 - an 8-layered board with a bias towards outer layer pairs.

In this layer stack, the copper on all four cores can be etched simultaneously and then sandwiched together (laminated) around layers of prepreg. This PCB would require the least complex manufacturing process.

2. Scenario 2 - an 8-Layered PCB with a bias towards inner layer pairs.

In this layer stack, the three cores can be etched simultaneously but then the outer prepreg and copper layers must be added separate, as part of the laminating process. The PCB as a whole must then pass through the etching process one more time to remove unwanted copper from the recently added outer layers.

3. Scenario 3 - an 8-Layered PCB created from a single core, built up with several prepreg layers.

In this layer stack, a single PCB core is progressively built up using multiple layers of prepreg and copper. Each time a new prepreg and copper layer is added, the PCB must past through the etching process again to remove unwanted copper from the recently added outer layer. This will occur sequentially for each of the 6 different prepreg layers. Because of the number of times the board has to pass through the copper etching process, this PCB would require the most complex manufacturing process. This process is normally only used when microvias (µVias) are required.

Vias

Main article: Defining the Via Types

Vias are used to span, or connect between the copper layers. If the via passes from the top surface of the board to the bottom surface, it is called a through hole via, thruhole via, or thru via. This type of via will include a land area, or ring of copper on each layer, which may or may not be used to connect to routing on that layer. These types of vias are mechanically drilled, once all of the layers are laminated together to form the board.

It is also possible to create vias that span other layers, by creating the vias at specific points during the fabrication process. These types of vias fall into two groups: blind and buried vias, and microvias (µVias). Each type has their own pros and cons, which are discussed below.

Blind and Buried Vias

Because the cores used in creating multi-layered PCBs can be etched, drilled and plated individually, before being laminated together into a complete stack, it is possible to create vias that are only connected to internal layers and which do not surface on one or even both sides of the final board. This means that the land area that otherwise would have been occupied by the via on the outer layers of the PCB can now be used for routing. Thes types of via are:

• Blind Vias - these are vias that only surface on one side of the PCB.
• Buried Vias - these are vias that don't surface on any side of the PCB.

Although the use of blind and buried vias is becoming increasingly common in advanced PCB designs, careful consideration needs to be given to the layer stackup of the PCB to ensure that the board is, in fact, able to be manufactured. Consider the layer stackup in the following image, that consists of 3 double-sided cores sandwiched around 2 prepreg layers. Consider also the via arrangement called for by an unwitting designer.

The via arrangement is impossible because it is not possible to drill (and plate) a hole that only passes through a prepreg layer. So in the image above, the 3rd and 5th vias (counting from the left) cannot be drilled. Using a standard multi-layer board fabrication process, the following via-layer pair combinations, would be possible.

To overcome this and be able to span other layer combinations other you would need a different approach, which is where µVias can come into play.

MicroVias

IPC-A - Microvia: (build-up via) defined as a blind structure with a maximum aspect ratio of 1:1 when measured in accordance with the image below, terminating on or penetrating a Target Land, with a total depth (X) of no more than 0.25 mm [9.84 mil], measured from the structure's Capture Land foil to the Target Land (show image).

µVias are used as the interconnects between layers in high density interconnect (HDI) designs, to accommodate the high input/output (I/O) density of advanced component packages and board designs. Sequential build-up (SBU) technology is used to fabricate HDI boards. The HDI layers are usually built up onto a traditionally manufactured double-sided core board or a multilayer PCB, as shown by the darker core section of the board in the image above (which also includes a blind via). As each HDI layer is built on to each side of the traditional PCB, µVias can be formed using: laser drilling, via formation, via metallization, and via filling. Because the hole is laser drilled, it has a cone shape.

If a connection required a path through multiple layers, the original approach was to stagger a series of µVias using a step-like pattern. Improvements in technology and processes now allow µVias to be stacked directly on top of each other.

Buried µVias are required to be filled, while blind µVias on the external layers do not require filling. Stacked µVias are usually filled with electroplated copper to make electrical interconnections between the multiple HDI layers and provide structural support for the outer level(s) of the µVia.

' Learn more about µVias

Rigid-Flex Boards

Main article: Rigid-Flex Design

Rigid-flex is the name given to a printed circuit that is a combination of both flexible circuit(s) and rigid circuit(s). This combination is ideal for exploiting the benefits of both flexible and rigid circuits - the rigid circuits can carry all or the bulk of the components, with the flexible sections acting as interconnections between the rigid sections.

Flex circuits are created from a stackup of flexible substrate material and copper, laminated together with adhesive, heat and pressure. The following image illustrates a simplified view of a flex circuit, with the constituent elements summarized thereafter:

  

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• Substrate - the most common substrate is polyimide, a strong, yet flexible thermosetting polymer (thermoset). Examples of polyimides often used in the manufacture of flexible circuits include:

  Apical,

  Kapton

  , 

  UPILEX

  , VTEC PI, Norton TH, and 

  Kaptrex

  . (Note that these are registered trade names, owned by their respective trademark holders).
• Copper - the copper layer is typically rolled and annealed (RA) copper, or sometimes wrought copper. These forms of copper are produced as a foil and offer excellent flexibility. They have an elongated grain, it is important to orient this correctly in a dynamic flex circuit to achieve the maximum flexing lifespan. This is achieved by orienting the dynamic flex circuit along the roll (so the circuit bends in the same way the foil was coiled on the roll). The flex manufacturer normally deals with this during the preparation of fabrication panels, it only becomes an issue if the designer performs their own circuit panelization (referred to as nesting in flex circuit design). The copper foil is typically coated with a photo-sensitive layer, which is then exposed and etched to give the desired pattern of conductors and termination pads.
• Adhesive - the adhesive is typically acrylic, and as the softest material in the structure, introduces the greatest number of manufacturing challenges. These include: squeeze-out, where the adhesive is squeezed out into openings cut into the cover layers to access copper layers; Z-axis expansion defects due to the higher CTE (coefficient of thermal expansion) of acrylic adhesive; and moisture out gassing due to the higher rate of moisture absorbance, which can result in resin recession, blow outs and delamination at plated through hole sites. Alternative adhesives and adhesive-less processes are available, these may be more appropriate in less cost-sensitive applications.

There are a number of standard stackups available for flex and rigid-flex circuits, referred to as Types. These are summarized below.

• Type 1 (Single Layer) - this type offers single-sided flexible wiring containing one conductive layer and one or two polyimide outer cover layers.

  

Functional Summary One conductive layer, either laminated between two insulating layers or uncovered on one side. Access holes to conductors can be on either one or both sides. No plating in component holes. Components, stiffeners, pins and connectors can be used. Suitable for static and dynamic flex applications.

• Type 2 (Double Layer) - this type offers double-sided flexible printed wiring, containing two conductive layers with plated through holes, with or without stiffeners.

  

Functional Summary Two conductive layers with an insulating layer between; outer layers can have covers or exposed pads. Plated through-holes provide connection between layers. Access holes or exposed pads without covers can be on either or both sides; vias can be covered on both sides. Components, stiffeners, pins and connectors can be used. Suitable for static and dynamic flex applications.

• Type 3 (Multilayer) - this type offers multilayer flexible printed wiring, containing three or more conductive layers with plated-through holes, with or without stiffeners.

  

Functional Summary Three or more flexible conductive layers with flexible insulating layers between each one; outer layers can have covers or exposed pads. Plated through-holes provide connection between layers. Access holes or exposed pads without covers can be on either or both sides. Vias can be blind or buried. Components, stiffeners, pins and connectors can be used. Typically used for static flex applications.

• Type 4 (Multilayer Rigid-Flex) - this type offers multilayer rigid and flexible material combinations (Rigid-Flex), containing three or more conductive layers with plated-through holes. Rigid-flex has conductors on the rigid layers, which differentiates it from multilayer circuits with stiffeners.

 

Functional Summary Three or more conductive layers with either flexible or rigid insulation material as insulators between each one; outer layers can have covers or exposed pads. Plated through-holes extend through both rigid and flexible layers (apart from blind and buried vias). Access holes or exposed pads without covers can be on either or both sides. Vias or interconnects can be fully covered for maximum insulation. Components, stiffeners, pins, connectors, heat sinks, and mounting brackets can be used.

• IPC B - Qualification and Performance Specification for Flexible Printed Boards.
• MIL-P-E - Military Specification: Printed Wiring Board, Flexible or Rigid-Flex, General Specification for.

The Types are defined in the following standards:

The PCB Manufacturing Process

The process of manufacturing a PCB is reasonably straightforward, and while it may vary slightly from manufacturer to manufacturer, understanding how this process operates will help you create PCBs that are less likely to suffer from manufacturing issues. A detailed step-by-step flow of the process used to manufacture standard multi-layer PCBs is given as a guide below.

1. Material Selection - the core and prepreg layers required for the final assembly are selected and cut to size.
2. Drill & Metalize Blind/Buried Vias - this step is only required if the board is to feature blind and/or buried vias. Drill vias and coat the via barrels with a metallization layer to ensure conduction through the core.
3. Laminate/Expose/Develop Photoresist - apply a photo-resistive coating to the copper clad cores. This is then exposed to UV light through a negative image of the layer's artwork. Once developed, the exposed photoresist will harden so that it is impervious to the etchant used in the next step. Unexposed photoresist is washed away leaving exposed copper underneath.
4. Etch - immerse in an acid bath to remove the unprotected copper.
5. Strip Resist - the photoresist used to protect the copper artwork is no longer required and is removed.
6. Laminate Cores together with Prepreg to create Panel - stack the cores, in order, on top of one another, with layers of prepreg in between.  When placed into a heated press, the prepreg will melt into an epoxy glue and will bind the core layers together to form a complete layer stack panel.
7. Drill & Metalize Holes/Vias - drill vias and holes through the complete panel and coat the barrels with a metallization layer to ensure conduction.
8. Laminate/Expose/Develop Photoresist - apply a photo-resistive coating to the outer layers. This is then exposed to UV light through a negative image of the outer layers' artwork. Once developed, the exposed photoresist will harden so that it is impervious to the etchant used in the next step. Unexposed photoresist is washed away leaving exposed copper underneath.
9. Etch - immerse in an acid bath to remove the unprotected copper.
10. Strip Resist - the photoresist used to protect the copper artwork is no longer required and is removed.
11. Print Solder Mask - print the solder mask onto the board to both protect the underlying copper artwork from oxidization, and prevent solder from adhering to unintended portions of the PCB.
12. Apply Surface Finish - apply a surface finish to exposed copper areas to both protect them from the elements, and provide a suitable surface for component mounting and soldering.
13. Print Silkscreen - print the silkscreen text and graphics onto the completed PCB.
14. Route - CNC Route the completed PCB to shape.
15. Pack and Ship Complete PCB - encase the PCB in packaging that will protect the PCB from moisture and corrosion, before shipping the completed PCB to its customer.

Visualizing the Manufacturing Process

The following sections provide a more graphical look at the process involved in fabricating the bare-board, for PCBs of differing layer counts.

Double-Sided Boards

1. Double-sided PCBs begin their life in much the same way as single-sided PCBs, except the core is coated with copper on both top and bottom surfaces.

2. The board is pre-drilled with all holes.

3. A photoresistive mask is then applied.

4. A negative image of the desired tracks is carefully aligned over the top of the photoresist.

5. The photoresistive coating is sensitive to light so when the board is illuminated under a powerful UV light, the exposed areas of photoresist harden.

6. The negative overlay is removed and the photoresist is developed.

7. The un-exposed portions of photoresist are washed away to reveal the copper layers below.

8. The board is then immersed in acid. The hardened photoresist protects the copper it covers, but the exposed copper is eaten away so that only copper tracks remain.

9. The hardened photoresist is then removed to expose the underlying copper traces.

10. Next, plating is chemically applied to the via and hole walls to ensure a conduction path between the top and bottom layers.

11. The copper is then coated with a thin layer of tin to help with solder adhesion, and a solder mask is applied to repel solder away from areas of the board that don't require it. The solder mask is typically what gives the PCB its green colour however other soldermask colours are also available.

4-Layer Boards

1. For 4-layer boards, the core is etched prior to drilling and then a layer of prepreg and copper are bonded to the outer surfaces using heat and high pressure.

2. The stack is then drilled and the outer layers etched, in much the same way as previously described for double-sided boards.

6-Layers and More

1. For boards that require 6 or more layers, core and prepreg layers will be interleaved to build up the required number of layers. The cores are all etched individually and then sandwiched together with layers of prepreg on the top and bottom, as well as bonding the two cores together. As with the 4-layer board, copper sheets are also attached to the top and bottom outer surfaces.

2. The stack is then drilled and the outer layers etched in much the same way as previously described for double-sided boards. This process can be extended in the same manner to create boards with 30 or more layers.

This process obtains the fabricated bare-board that will then proceed - after requisite visual inspections and bare-board testing by the customer - to the Assembly house, at which time the PCB will be assembled using Pick and Place machines, and in accordance with the supplied Pick and Place and Bill of Materials manufacturing output. It is typical after assembly to also conduct in-circuit assembly testing.

The process described above does not cover flexible circuit board manufacture, or the sequential buildup (SBU) process that uses µVias.

• Learn more about flexible printed circuit manufacture on the Tech-Etch site, or download their Flexible Circuit Design Guide
• Learn more about SBU technology on the HDI Handbook website

Where to Now?

Main article: Defining the Layer Stack

No matter what type of PCB you are wanting to manufacture - be it rigid, or rigid-flex - the first thing to do is to define the layer stackup as required. Within Altium NEXUS's PCB Editor, all layer stacks are defined in the Layer Stack Manager (Design » Layer Stack Manager). For a new board, its single default stack comprises: a dielectric core, 2 copper (signal) layers, as well as the top and bottom solder mask/coverlay layers, as shown in the image below.

For more information on defining the layer stack for your board in Altium NEXUS, see Defining the Layer Stack.

The Layer Stack Manager not only caters for the definition of a single layer stack, for standard single-sided, double-sided, or multi-layer boards, but also facilitates the definition of multiple stacks, in support of rigid-flex designs. For more information on designing your boards with flexibility, see Rigid-Flex Design

 

Printed Circuit Board (PCB) Basics

Layers and their Stackup

In this class we will be building boards with four conductive layers --- so-called 4-layer boards. These boards are a lamination of various conductive and non-conductive layers. Essentially, PCBs are constructed from multiple layers of thin fiberglass. Some layers (known as "cores") are coated on one or both sides with copper foil and others are bare fiberglass (known as "prepreg" -- preimpregnated fiberclass cloth -- essentially a woven glass matt of given weave properties impregnated with a polyester epoxy resin). The thickness of each layer lies in the range from several mils to tens of mils. Layer thickness and stackup is chosen so as to have the required overall electrical properties and dimensions. Electrical connections are formed by etching patterns into the copper layers. The patterns are formed using masks and photographic techniques. The fabrication of 4-layer boards for this class requires, at a minimum, the seven masks listed below:

• Topside silkscreen -- specifies the pattern of (white) paint on the topside that will be applied via a silkscreen-like technique. It is important that the component reference designators and component outlines be drawn on this layer.
• Topside soldermask -- identifies the places (openings in the green soldermask layer) on the topside where component pins can be soldered to the board.
• Top traces -- the pattern of conductive traces on the topside of the board.
• Inner plane #1 a mostly copper region that is normally tied to GND and also known as the "ground plane".
• Inner plane #2 a mostly copper region (one of the inside planes of the board) that is normally used to provide efficient access to one or more DC voltages). Obviously, when more than voltage is present the "plane" is subdivided into distinct non-intersecting copper polygons.
• Bottomside soldermask -- specifies the soldermask openings for the bottom side of the board.
• Bottomside silkscreen -- same idea as the topside silkscreen except for the bottom of the board.

For this class, the boards will be assembled by hand, so-called custom hand assembly. For this we need just the seven masks listed above rather than nine. If our designs were going to be mass-produced then at least two additional masks would be required:

• Topside solderpaste mask
• Bottomside solderpaste mask

These additional masks specify the shapes and locations where solder paste would be dispensed in support of automated assembly. Since we are making a very small number of copies of our boards and since the soldering is all being done by hand these solderpaste masks are not needed.

Holes in PCBs

Most printed circuit boards have holes drilled in them. There are several types of holes described below. The older PCB technology, primarily supporting components with leads requiring a hole for each pin, is known as "through hole" or "PTH" (plated through hole) technology whereas the more modern style that utilizes denser surface-mounted components takes the name "SMT" or "surface-mount technology". The primary difference between these styles is the number of, size of, and usage of holes. Note that PTH and SMT components can be freely intermixed on a board. The types of holes and the terminology follows:

• Via: The word "via" literally means "way" --- a way to make a connection between layers in a PCB. Vias are typically the smallest holes on the board; they are normally all the same size. For our class, vias consist of a 16 mil drill hole, surrounded by a 34 mil conductive "pad" and they are plated through so as to connect a trace on the topside to another trace on the bottom of the board. Since there is no component lead going through a via hole vias can actually be made even smaller. We have chosen the 34-mil size to improve PCB yield as well as to facilitate debugging (note that 30-gauge wire-wrap wire can be inserted into a via to provide a convenient, though unplanned, test point).
• Through hole: This term doesn't require much definition because its name says it all, though today's technology does include the campability for having holes that go only part of the way through a board (so-called "blind vias"). Through holes are holes that go completely through the board. They are most often plated through so that there is a conductive path from one side to the other (when plated, they are also known as "plated through holes" or "PTH").
• Tooling hole: Also known as a "mounting hole", this term refers to a hole in a printed circuit board that is used to attach the board to a test fixture or to its operational location. Often tooling holes are non-plated through, meaning that they remain insolated from any electrical components or traces on the board.

Holes have an implicit interaction with each of the PCB layers they pass through. As a plated-through hole carrying a signal passes through a ground plane, a (negative) clearance pad is used to ensure that the copper ground plane is kept well separated from the signal that is passing through. Similar clearance pads are also used on power plane layers. Clearance pads must be larger in diameter than the drilled hole (by approximately 15 mils).

But what do we do when we want to make a connection between a trace on either the topside or bottomside and one of the inner planes? It would be sufficient to merely omit the clearance pad; that would result in a solid connection between the plated wall of the through hole and the copper plane. Since inner planes are intended to be used for power supply and ground connections, however, we expect relatively large currents to flow in these locations. Usually, these planes are made thicker, so that they can handle higher currents. And, since copper is an excellent conductor of heat, the power and ground planes also provide a heat-spreading or heat-sinking effect. This can make it extra difficult to solder to pins that connect to planes .... they can take a great deal of heat. To improve the solderability of pins that connect to planes, we normally provide a tiny "expansion joint" at these locations. The implementation of such a joint is known as a thermal pad, or more simply, just a thermal. The image below shows a region of an inner plane with some thermals of various sizes. You can recognize them by their "X"-shaped structure. In this image, the green material represents copper and the black areas represent no copper. The hole in the middle of each thermal will be drilled out, leaving a plated-through attachment between the voltage on the plane and whatever is connected to the through-hole on the topside and/or bottomside. The structures that look like a donut (with no "X" across) are a type of clearance pads. They isolate the plated-through hole from the plane to ensure that no connection is made.

The two lines with via holes on each end are traces with isolation around them. Once a plane region has been isolated by surrounding it with non-copper space, it can be used like a regular outer plane, including routed traces. It is normally better to use the inner planes for power and ground connections --- i.e. as planes --- but there are sometimes good reasons to include routing on these planes.

Packages and Component Footprints

Printed circuit boards are all about circuits, i.e. interconnections among electronic components. Most components are soldered to PCBs. In order to provide the right environment for soldering to be effective, the leads of a component must make reliable contact (both electrical and mechanical) to the etched copper traces. Each component must have an appearance on the board; this appearance is referred to as the component's land pattern. A component's land pattern is a set of etched copper features that directly corresponds to the leads of the component. These features are normally made a bit larger than the component leads so there is space for the solder. In the Mentor Graphics tools, these land patterns arise as "cells". There is a tutorial within the Library Manager section about how to make a "cell" as well as how to use them in a design.

Below is a list of packages (incomplete) currently used in the electronics industry.

• Dual in-line (DIP) or Plastic DIP (PDIP): These packages are among the most mature IC packages in use today. They are rectangular in shape with leads emerging on the two longest sides, forming two parallel lines. These packages utilize plated through hole (PTH) technology as each lead requires a hole in the PCB. Typical lead counts range from 8 to 48. The separation between adjacent leads (which we call the lead pitch) in dual in-line packages is normally 100 mils.
• Small-Outline Integrated Circuit (SOIC): The SOIC is a popular rectangular surface-mounted IC package with 8 or more so-called "gull-wing" leads. The leads emerge on the two long sides, forming two parallel rows much like DIPs though without any holes required. Typical body widths are 150 mils (so-called "narrow SOICs") or 300 mils ("wide body SOICs") and the most typical lead pitch is 50 mils (1.27 mm).
• Shrink Small-Outline Package (SSOP): The SSOP is a smaller (so-called "shrink" version) of the SOIC. Lead counts range from 8 to 64 and the lead pitches are more aggressive, ranging from 50 mils down to 25 mils. Typical body widths are 150 mils, 209 mils, or 300 mils.
• Thin Shrink Small-Outline Package (TSSOP): The TSSOP package is even smaller than the SSOP. The body of TSSOP packages is also thinner than otherwise-corresponding SSOP packages. Lead counts range from 8 to 80 and the lead pitches are very aggressive, ranging from 25 mils down to 15 mils. There are several body sizes but we do not encourage use of TSSOP packages due to issues that arise with assembly, debugging, and rework. The TSSOP is on the list of forbidden (or at least discouraged) package types for ECE189. You should avoid using it.
• Small-Outline J-lead Package (SOJ): The SOJ package is exactly like the SOIC except that the leads emerge from the sides and turn under the package; they are shaped like a "J". SOJ packages are a bit more difficult to solder down but they were invented so that they could be supported by sockets. Sockets are useful when the integrated circuit must be removable such as would be the case for a ROM or flash memory that needs to be taken to a programmer to be written. When a package with J-leads has leads on all four sides, it is called an LCC or PLCC as described below.
• Quad Flat No-Lead (QFN) Package: The QFN is a two- or four-sided leadless chip package that is (unfortunately) becoming increasingly popular with chip vendors. The popularity is presumably due to its excellent electrical properties, though the soldering, debugging, and handling properties leave a bit to be desired. The QFN is currently on the do-not-use-for-ECE189 list because in the last few years every single time we have attempted to use it we have encountered significant issues. Please avoid selecting a part in this type of package.
• Leaded Chip Carrier (LCC) or Plastic LCC (PLCC): A leaded chip carrier (LCC) or the plastic version of the same thing (PLCC) is similar to an SOJ package except that there are leads on all four sides. It supports sockets and typical lead counts are from 20 to 84. This package has some flexibility in that it can be directly soldered onto the PCB or it can be used with a socket.
• Quad Flat Pack (QFP) or Plastic QFP (PQFP): Integrated circuits with high lead counts typically use a package like the ceramic QFP or the plastic version (PQFP). These packages have leads on four sides. The leads are of the gull-wing style such as are used in SOICs though they tend to be smaller and much more tightly packed. Lead counts in QFPs typically range from 44 up to well above 200. Lead pitch varies widely with 1.0 mm (39 mils), 0.80 mm (31.4 mils), 0.65 mm (25.6 mils), and 0.5 mm (19.6 mils) being the most typical. In selecting your processor (which will most likely come in some sort of QFP) be careful to avoid the more aggressive tight-pitch varieties. Your debugging will be much much easier if you use a slightly larger package.
• Ball Grid Array (BGA): Integrated circuits with very high lead counts often come in ball grid array (BGA) packages. Three BGA packages are shown above. The leftmost one is a top view whereas the others are bottom views of the packages. BGA packages are popular because they are very dense, thus saving board space. They are on the "forbidden list" for ECE189, however. That means you may not use them. The reasons for this are many but the primary issue is cost. Special equipment is required to install or rework these packages. Such equipment is currently not available on campus so any manipulation involving a BGA package would require a trip to the assembler and an extra charge of $50 to $100. Another reason we have chosen to forbid BGAs is that there is absolutely no access to signals once the packages have been mounted on the board. Everything happens entirely underneath the part. This makes debugging impossible. Bottom line: you may not use BGAs in ECE189.
• Chip-Scale Package (CSP): The chip-scale package is an example of a very tiny (hence the name "chip-scale") package that we cannot use in this class. Packages like this are intended primarily for very high-density (and often high volume) applications like inside cell phones. CSPs are, essentially, just chip-level BGAs. The images above illustrate the tiny size by showing them relative to a pencil eraser or a cell keyboard. You may not use CSPs in ECE189.
• Packages: For surface-mounted resistors and capacitors (and also sometimes LEDs and other 2-terminal devices) there is a series of standard packages whose sizes are given in units of 0.01 inch. One such package is the which means that it measures 80 mils by 50 mils. A slightly larger variety in the same general family is (120 mils by 60 mils). and packages are easy to work with and their use in this class is encouraged. Smaller two-terminal SMT devices such as , , or are not allowed. They are, simply, too small to deal with and their use for our class purposes would drive our assembly costs considerably higher.

Forbidden Packages for ECE189 Projects

For cost, handling, and debugging reasons we do not allow use in this class of some of the more aggressive electronic packaging that is available on the market. A partial list of forbidden packages follows:

• No SMT resistors or capacitors smaller than size (80 mils x 50 mils). This forbidden list includes , , and the almost invisible package sizes. The and larger sizes are fine and can be used without problems.
• No QFN packages of any type. In past years various groups have attempted to use these. We have had a great deal of trouble with these packages because all of the land patterns are completely covered by the component, once installed. Not only is it difficult for the assembler to solder the components down in the first place but it is nearly impossible for us to make any changes whatsoever. You may not believe this, but we often find errors in the initial ECE189 student designs . Sometimes these errors aren't discovered until after the boards have been made and assembled. We workaround such errors by making patches to the board. With QFN packages, any such patches or changes are extremely difficult if not impossible for us to do without taking the whole board back to the assembler.
• No ball grid array (BGA) packages. For many of the same reasons cited above, the debugging and rework issues associated with BGAs prevent us from allowing these packages on ECE189 boards. Mounting and reworking boards with BGA packages requires special equipment that is only available at the assembler. We cannot do it on-campus. Like QFN packages, debugging with BGAs is next to impossible.
• While not strictly forbidden, you should avoid the densest examples of SSOP, TSSOP, and similar packaging. In this case it is the lead pitch (separation between adjacent component leads) that matters. We'd like to deal with pitches greater than 30 mils (about 0.8 mm) whenever possible. Some microprocessors and memories come only in packages that use a lead pitch of 25 mils so, if one of these is your chosen processor, we can allow it. But, be warned(!) that as the lead pitch goes down, your debugging job gets much more difficult. We strongly advise against using aggressively pitched packages in your ECE189 project. You can often find equivalent parts that are packaged in larger, less aggressive packages. By selecting larger packages you will make your life far easier in spring quarter when you are debugging the project.

Solder Masks

As component packaging shrinks in size, the effort required to solder components on boards increases dramatically. The soldermask layer is a tough semi-transparent material coated on both sides of a PCB. It is what makes the PCB green (actually soldermasks come in other colors as well but the boards for this class will always be green). The purpose of the soldermask is to define the regions where components can be soldered to pads or traces. The soldermask has openings directly over each of the spots where a component lead touches its land pattern on the board. When there are multiple component leads densely packed in a row it is the soldermask that helps to prevent solder bridges (unwanted extra connections between adjacent solder points).

Silkscreens

The last layers that go onto your PCB during the manufacturing process are the silkscreens (sometimes referred to as legends). There may be slikscreens for the topside, the bottomside, or none at all. The silkscreen layers specify any painted graphics (normally white in color) that are to appear. In an effort to keep our budgets under control we normally request only a topside silkscreen though if your project has components that need to be soldered on the bottomside it will be necessary to request a bottomside silkscreen as well.

Silkscreens may have just about any graphical content --- e.g. logos, project name, designer name(s) --- though there are certain expectations associated with the electronic assembly process. One expectation is that each and every component should have its unique reference designator (aka "refdes") printed nearby the component footprint and there must be some sort of outline or clear indication on the silkscreen to indicate how the component is to be oriented (e.g. where its pin #1 is located). For polarized parts such as diodes, LEDs, electrolytic capacitors, etc., it is imperative that the polarity is marked on the board (via the silkscreen). It is customary to place a small "+" sign and/or a "-" sign near the appropriate pin of polarized parts. Often these outlines and refdes positions are a built-in part of each "cell" and if you make your own cells you must be sure to include them.

The assembler relies on the reference designators to find each part in its little bag that is in the parts kit we provide him. This single marking on the board is the only link between the parts kits, the bill of materials, and the bare printed circuit boards. If your board has one or more components that are not identified by their reference designators on the silkscreen, then the assembler will simply skip them. The refdes field is a critical link for assembly. The assembler will simply ignore any "extra" parts kit components.

How printed circuit boards are made and assembled

Here is a short video (running just under 5 minutes) that shows how printed circuit boards are made and assembled. If you have trouble with the embedded viewer, try an external viewer here.

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